/************************************************************** * The following table was created based on Microchip's * PIC18LF4321 processor header and include file. It contains * all registers and bits defined in the p18f4321 header by the * line: #include . All registers are arranged in * alphabetical order. * * Table of contents: * * Registers * * # Some useful macros for inline assembly stuff * * ;=============================================== * ; Configuration selections available for the PIC18LF4321 * ;=============================================== * *************************************************************/ ADCON0 ADCON0bits 0: ADON 1: GO DONE NOT_DONE GO_DONE 2: CHS0 3: CHS1 4: CHS2 5: CHS3 ADCON1 ADCON1bits 0: PCFG0 1: PCFG1 2: PCFG2 3: PCFG3 4: VCFG0 5: VCFG1 ADCON2 ADCON2bits 0: ADCS0 1: ADCS1 2: ADCS2 3: ACQT0 4: ACQT1 5: ACQT2 6: 7: ADFM ADRES ADRESH ADRESL BAUDCON BAUDCONbits 0: ABDEN 1: WUE 2: 3: BRG16 4: SCKP TXCKP 5: RXDTP 6: RCIDL RCMT 7: ABDOVF BAUDCTL BAUDCTLbits 0: ABDEN 1: WUE 2: 3: BRG16 4: SCKP TXCKP 5: RXDTP 6: RCIDL RCMT 7: ABDOVF BSR CCP1CON CCP1CONbits 0: CCP1M0 1: CCP1M1 2: CCP1M2 3: CCP1M3 4: DC1B0 CCP1Y 5: DC1B1 CCP1X 6: P1M0 7: P1M1 CCP2CON CCP2CONbits 0: CCP2M0 1: CCP2M1 2: CCP2M2 3: CCP2M3 4: DC2B0 CCP2Y 5: DC2B1 CCP2X CCPR1 CCPR1H CCPR1L CCPR2 CCPR2H CCPR2L CMCON CMCONbits 0: CM0 1: CM1 2: CM2 3: CIS 4: C1INV 5: C2INV 6: C1OUT 7: C2OUT CVRCON CVRCONbits 0: CVR0 1: CVR1 2: CVR2 3: CVR3 4: CVRSS 5: CVRR 6: CVROE 7: CVREN ECCP1AS ECCP1ASbits 0: PSSBD0 1: PSSBD1 2: PSSAC0 3: PSSAC1 4: ECCPAS0 5: ECCPAS1 6: ECCPAS2 7: ECCPASE ECCP1CON ECCP1CONbits 0: CCP1M0 1: CCP1M1 2: CCP1M2 3: CCP1M3 4: DC1B0 CCP1Y 5: DC1B1 CCP1X 6: P1M0 7: P1M1 ECCP1DEL ECCP1DELbits 0: PDC0 1: PDC1 2: PDC2 3: PDC3 4: PDC4 5: PDC5 6: PDC6 7: PRSEN EEADR EECON1 EECON1bits 0: RD 1: WR 2: WREN 3: WRERR 4: FREE 5: 6: CFGS 7: EEPGD EECON2 EEDATA FSR0 FSR0H FSR0L FSR1 FSR1H FSR1L FSR2 FSR2H FSR2L HLVDCON HLVDCONbits 0: LVDL0 LVV0 1: LVDL1 LVV1 2: LVDL2 LVV2 3: LVDL3 LVV3 4: LVDEN 5: IRVST BGST 6: 7: VDIRMAG INDF0 INDF1 INDF2 INTCON INTCON2 INTCON2bits 0: RBIP 1: 2: TMR0IP 3: 4: INTEDG2 5: INTEDG1 6: INTEDG0 7: RBPU NOT_RBPU INTCON3 INTCON3bits 0: INT1IF INT1F 1: INT2IF INT2F 2: 3: INT1IE INT1E 4: INT2IE INT2E 5: 6: INT1IP INT1P 7: INT2IP INT2P INTCONbits 0: RBIF 1: INT0IF 2: TMR0IF T0IF 3: RBIE 4: INT0IE 5: TMR0IE T0IE 6: PEIE GIEL 7: GIE GIEH IPR1 IPR1bits 0: TMR1IP 1: TMR2IP 2: CCP1IP 3: SSPIP 4: TXIP 5: RCIP 6: ADIP 7: PSPIP IPR2 IPR2bits 0: CCP2IP 1: TMR3IP 2: LVDIP HLVDIP 3: BCLIP 4: EEIP 5: 6: CMIP 7: OSCFIP LATA LATAbits 0: LATA0 1: LATA1 2: LATA2 3: LATA3 4: LATA4 5: LATA5 6: LATA6 7: LATA7 LATB LATBbits 0: LATB0 1: LATB1 2: LATB2 3: LATB3 4: LATB4 5: LATB5 6: LATB6 7: LATB7 LATC LATCbits 0: LATC0 1: LATC1 2: LATC2 3: LATC3 4: LATC4 5: LATC5 6: LATC6 7: LATC7 LATD LATDbits 0: LATD0 1: LATD1 2: LATD2 3: LATD3 4: LATD4 5: LATD5 6: LATD6 7: LATD7 LATE LATEbits 0: LATE0 1: LATE1 2: LATE2 LVDCON LVDCONbits LVDCONbits 0: LVDL0 LVV0 1: LVDL1 LVV1 2: LVDL2 LVV2 3: LVDL3 LVV3 4: LVDEN 5: IRVST BGST 6: 7: VDIRMAG OSCCON OSCCONbits 0: SCS0 1: SCS1 2: IOFS FLTS 3: OSTS 4: IRCF0 5: IRCF1 6: IRCF2 7: IDLEN OSCTUNE OSCTUNEbits 0: TUN0 1: TUN1 2: TUN2 3: TUN3 4: TUN4 5: 6: PLLEN 7: INTSRC PC PCL PCLATH PCLATU PIE1 PIE1bits 0: TMR1IE 1: TMR2IE 2: CCP1IE 3: SSPIE 4: TXIE 5: RCIE 6: ADIE 7: PSPIE PIE2 PIE2bits 0: CCP2IE 1: TMR3IE 2: LVDIE HLVDIE 3: BCLIE 4: EEIE 5: 6: CMIE 7: OSCFIE PIR1 PIR1bits 0: TMR1IF 1: TMR2IF 2: CCP1IF 3: SSPIF 4: TXIF 5: RCIF 6: ADIF 7: PSPIF PIR2 PIR2bits 0: CCP2IF 1: TMR3IF 2: LVDIF HLVDIF 3: BCLIF 4: EEIF 5: 6: CMIF 7: OSCFIF PLUSW0 PLUSW1 PLUSW2 PORTA PORTAbits 0: RA0 AN0 C1N 1: RA1 AN1 C2N 2: RA2 AN2 C2P VREFM CVREF 3: RA3 AN3 C1P VREFP 4: RA4 C1OUT T0CKI 5: RA5 AN4 C2OUT HLVDIN NOT_SS 6: RA6 OSC2 CLKO 7: RA7 OSC1 CLKI PORTB PORTBbits 0: RB0 INT0 AN12 FLT0 1: RB1 INT1 AN10 2: RB2 INT2 AN8 3: RB3 CCP2 AN9 4: RB4 KBI0 AN11 5: RB5 KBI1 PGM 6: RB6 KBI2 PGC 7: RB7 KBI3 PGD PORTC PORTCbits 0: RC0 T1OSO T13CKI T1CKI 1: RC1 T1OSI CCP2 2: RC2 CCP1 P1A 3: RC3 SCK SCL 4: RC4 SDI SDA 5: RC5 SDO 6: RC6 TX CK 7: RC7 RX DT PORTD PORTDbits 0: RD0 PSP0 1: RD1 PSP1 2: RD2 PSP2 3: RD3 PSP3 4: RD4 PSP4 5: RD5 PSP5 P1B 6: RD6 PSP6 P1C 7: RD7 PSP7 P1D PORTE PORTEbits 0: RE0 RD NOT_RD AN5 1: RE1 WR NOT_WR AN6 2: RE2 CS NOT_CS AN7 3: RE3 MCLR NOT_MCLR VPP POSTDEC0 POSTDEC1 POSTDEC2 POSTINC0 POSTINC1 POSTINC2 PR2 PREINC0 PREINC1 PREINC2 PROD PRODH PRODL PWM1CON PWM1CONbits 0: PDC0 1: PDC1 2: PDC2 3: PDC3 4: PDC4 5: PDC5 6: PDC6 7: PRSEN RCON RCONbits 0: BOR NOT_BOR 1: POR NOT_POR 2: PD NOT_PD 3: TO NOT_TO 4: RI NOT_RI 5: 6: SBOREN 7: IPEN RCREG RCSTA RCSTAbits 0: RX9D 1: OERR 2: FERR 3: ADEN ADDEN 4: CREN 5: SREN 6: RX9 7: SPEN SPBRG SPBRGH SSPADD SSPBUF SSPCON1 SSPCON1bits 0: SSPM0 1: SSPM1 2: SSPM2 3: SSPM3 4: CKP 5: SSPEN 6: SSPOV 7: WCOL SSPCON2 SSPCON2bits 0: SEN 1: RSEN ADMSK1 2: PEN ADMSK2 3: RCEN ADMSK3 4: ACKEN ADMSK4 5: ACKDT ADMSK5 6: ACKSTAT 7: GCEN SSPSTAT SSPSTATbits 0: BF 1: UA 2: R W NOT_W R_W NOT_WRITE 3: S 4: P 5: D A NOT_A D_A NOT_ADDRESS 6: CKE 7: SMP STATUS STATUSbits 0: C 1: DC 2: Z 3: OV 4: N STKPTR STKPTRbits 0: SP0 1: SP1 2: SP2 3: SP3 4: SP4 5: 6: STKUNF 7: STKFUL STKOVF T0CON T0CONbits 0: T0PS0 1: T0PS1 2: T0PS2 3: PSA 4: T0SE 5: T0CS 6: T08BIT T016BIT 7: TMR0ON T1CON T1CONbits 0: TMR1ON 1: TMR1CS 2: T1SYNC NOT_T1SYNC 3: T1OSCEN 4: T1CKPS0 5: T1CKPS1 6: T1RUN 7: RD16 T2CON T2CONbits 0: T2CKPS0 1: T2CKPS1 2: TMR2ON 3: TOUTPS0 T2OUTPS0 4: TOUTPS1 T2OUTPS1 5: TOUTPS2 T2OUTPS2 6: TOUTPS3 T2OUTPS3 T3CON T3CONbits 0: TMR3ON 1: TMR3CS 2: T3SYNC NOT_T3SYNC 3: T3CCP1 4: T3CKPS0 5: T3CKPS1 6: T3CCP2 7: RD16 TABLAT TBLPTR TBLPTRH TBLPTRL TBLPTRU TMR0H TMR0L TMR1H TMR1L TMR2 TMR3H TMR3L TOS TOSH TOSL TOSU TRISA TRISAbits 0: TRISA0 1: TRISA1 2: TRISA2 3: TRISA3 4: TRISA4 5: TRISA5 6: TRISA6 7: TRISA7 TRISB TRISBbits 0: TRISB0 1: TRISB1 2: TRISB2 3: TRISB3 4: TRISB4 5: TRISB5 6: TRISB6 7: TRISB7 TRISC TRISCbits 0: TRISC0 1: TRISC1 2: TRISC2 3: TRISC3 4: TRISC4 5: TRISC5 6: TRISC6 7: TRISC7 TRISD TRISDbits 0: TRISD0 1: TRISD1 2: TRISD2 3: TRISD3 4: TRISD4 5: TRISD5 6: TRISD6 7: TRISD7 TRISE TRISEbits 0: TRISE0 1: TRISE1 2: TRISE2 3: 4: PSPMODE 5: IBOV 6: OBF 7: IBF TXREG TXSTA TXSTAbits 0: TX9D 1: TRMT 2: BRGH 3: SENDB 4: SYNC 5: TXEN 6: TX9 7: CSRC W WDTCON WDTCONbits 0: SWDTEN SWDTE WREG /*------------------------------------------------------------------------- * Some useful defines for inline assembly stuff *-------------------------------------------------------------------------*/ #define ACCESS 0 #define BANKED 1 /*------------------------------------------------------------------------- * Some useful macros for inline assembly stuff *-------------------------------------------------------------------------*/ #define Nop() {_asm nop _endasm} #define ClrWdt() {_asm clrwdt _endasm} #define Sleep() {_asm sleep _endasm} #define Reset() {_asm reset _endasm} #define Rlcf(f,dest,access) {_asm movlb f rlcf f,dest,access _endasm} #define Rlncf(f,dest,access) {_asm movlb f rlncf f,dest,access _endasm} #define Rrcf(f,dest,access) {_asm movlb f rrcf f,dest,access _endasm} #define Rrncf(f,dest,access) {_asm movlb f rrncf f,dest,access _endasm} #define Swapf(f,dest,access) {_asm movlb f swapf f,dest,access _endasm } ;========================================================================== ; Configuration selections available for the PIC18LF4321 ; ; Example of usage: ; #pragma config OSC = INTIO1 ; ; Oscillator Selection bits: ; OSC = LP LP Oscillator ; OSC = XT XT Oscillator ; OSC = HS HS Oscillator ; OSC = RC External RC oscillator, CLKO function on RA6 ; OSC = EC EC oscillator, CLKO function on RA6 ; OSC = ECIO EC oscillator, port function on RA6 ; OSC = HSPLL HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) ; OSC = RCIO External RC oscillator, port function on RA6 ; OSC = INTIO2 Internal oscillator block, port function on RA6 and RA7 ; OSC = INTIO1 Internal oscillator block, CLKO function on RA6, port function on RA7 ; ; Fail-Safe Clock Monitor Enable bit: ; FCMEN = OFF Fail-Safe Clock Monitor disabled ; FCMEN = ON Fail-Safe Clock Monitor enabled ; ; Internal/External Oscillator Switchover bit: ; IESO = OFF Oscillator Switchover mode disabled ; IESO = ON Oscillator Switchover mode enabled ; ; Power-up Timer Enable bit: ; PWRT = ON PWRT enabled ; PWRT = OFF PWRT disabled ; ; Brown-out Reset Enable bits: ; BOR = OFF Brown-out Reset disabled in hardware and software ; BOR = SOFT Brown-out Reset enabled and controlled by software (SBOREN is enabled) ; BOR = NOSLP Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) ; BOR = ON Brown-out Reset enabled in hardware only (SBOREN is disabled) ; ; Brown-out Reset Voltage bits: ; BORV = 0 Maximum Setting ; BORV = 1 ; BORV = 2 ; BORV = 3 Minimum Setting ; ; Watchdog Timer Enable bit: ; WDT = OFF WDT disabled (control is placed on the SWDTEN bit) ; WDT = ON WDT enabled ; ; Watchdog Timer Postscale Select bits: ; WDTPS = 1 1:1 ; WDTPS = 2 1:2 ; WDTPS = 4 1:4 ; WDTPS = 8 1:8 ; WDTPS = 16 1:16 ; WDTPS = 32 1:32 ; WDTPS = 64 1:64 ; WDTPS = 128 1:128 ; WDTPS = 256 1:256 ; WDTPS = 512 1:512 ; WDTPS = 1024 1:1024 ; WDTPS = 2048 1:2048 ; WDTPS = 4096 1:4096 ; WDTPS = 8192 1:8192 ; WDTPS = 16384 1:16384 ; WDTPS = 32768 1:32768 ; ; MCLR Pin Enable bit: ; MCLRE = OFF RE3 input pin enabled; MCLR disabled ; MCLRE = ON MCLR pin enabled; RE3 input pin disabled ; ; Low-Power Timer1 Oscillator Enable bit: ; LPT1OSC = OFF Timer1 configured for higher power operation ; LPT1OSC = ON Timer1 configured for low-power operation ; ; PORTB A/D Enable bit: ; PBADEN = DIG PORTB<4:0> pins are configured as digital I/O on Reset ; PBADEN = ANA PORTB<4:0> pins are configured as analog input channels on Reset ; ; CCP2 MUX bit: ; CCP2MX = RB3 CCP2 input/output is multiplexed with RB3 ; CCP2MX = RC1 CCP2 input/output is multiplexed with RC1 ; ; Stack Full/Underflow Reset Enable bit: ; STVREN = OFF Stack full/underflow will not cause Reset ; STVREN = ON Stack full/underflow will cause Reset ; ; Single-Supply ICSP Enable bit: ; LVP = OFF Single-Supply ICSP disabled ; LVP = ON Single-Supply ICSP enabled ; ; Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit: ; ICPORT = OFF ICPORT disabled ; ICPORT = ON ICPORT enabled ; ; Boot Block Size Select bits: ; BBSIZ = BB256 256 Word ; BBSIZ = BB512 512 Word ; BBSIZ = BB1K 1024 Word ; ; Extended Instruction Set Enable bit: ; XINST = OFF Instruction set extension and Indexed Addressing mode disabled (Legacy mode) ; XINST = ON Instruction set extension and Indexed Addressing mode enabled ; ; Background Debugger Enable bit: ; DEBUG = ON Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug ; DEBUG = OFF Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins ; ; Code Protection bit Block 0: ; CP0 = ON Block 0 code-protected ; CP0 = OFF Block 0 not code-protected ; ; Code Protection bit Block 1: ; CP1 = ON Block 1 code-protected ; CP1 = OFF Block 1 not code-protected ; ; Boot Block Code Protection bit: ; CPB = ON Boot block code-protected ; CPB = OFF Boot block not code-protected ; ; Data EEPROM Code Protection bit: ; CPD = ON Data EEPROM code-protected ; CPD = OFF Data EEPROM not code-protected ; ; Write Protection bit Block 0: ; WRT0 = ON Block 0 write-protected ; WRT0 = OFF Block 0 not write-protected ; ; Write Protection bit Block 1: ; WRT1 = ON Block 1 write-protected ; WRT1 = OFF Block 1 not write-protected ; ; Configuration Register Write Protection bit: ; WRTC = ON Configuration registers (300000-3000FFh) write-protected ; WRTC = OFF Configuration registers (300000-3000FFh) not write-protected ; ; Boot Block Write Protection bit: ; WRTB = ON Boot block write-protected ; WRTB = OFF Boot block not write-protected ; ; Data EEPROM Write Protection bit: ; WRTD = ON Data EEPROM write-protected ; WRTD = OFF Data EEPROM not write-protected ; ; Table Read Protection bit Block 0: ; EBTR0 = ON Block 0 protected from table reads executed in other blocks ; EBTR0 = OFF Block 0 not protected from table reads executed in other blocks ; ; Table Read Protection bit Block 1: ; EBTR1 = ON Block 1 protected from table reads executed in other blocks ; EBTR1 = OFF Block 1 not protected from table reads executed in other blocks ; ; Boot Block Table Read Protection bit: ; EBTRB = ON Boot block protected from table reads executed in other blocks ; EBTRB = OFF Boot block not protected from table reads executed in other blocks ; ;==========================================================================